Technical Field
This disclosure relates to electronic design automation (EDA) tools. More specifically, this disclosure relates to goal-based cell partitioning in the presence of obstacles.
Related Art
Advances in process technology and a practically unlimited appetite for consumer electronics have fueled a rapid increase in the size and complexity of integrated circuit (IC) designs. The performance of EDA tools is very important because it reduces the time to market for IC designs. Layout verification is an important stage in an EDA design flow that involves performing design rule check (DRC) and layout versus schematic (LVS) check on the circuit design layout.
Unfortunately, due to the rapid increase in the size and complexity of IC designs, conventional layout verification tools can require a very long time to perform verification.